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TDC1016
Video Speed D/A Converter
10-Bit, 20 Msps Features
* * * * * * * * 20 Msps conversion rate 8, 9, or 10-bit linearity Voltage output, no amplifier required Single supply operation (-5.2V, ECL compatible) Dual supply operation (5.0V, TTL compatible) Internal 10-bit latched data register Low glitch energy Disabling controls, forcing full-scale, zero, and inverting input data * Binary or two's complement input data formats * Differential gain = 1.5%, differential phase = 1.0
Description
The TDC1016 is a bipolar monolithic digital-to-analog converter which can convert digital data into an analog voltage at rates up to 20 Msps (Megasamples Per Second). The device includes an input data register and operates without an external deglitcher or amplifier. Operating the TDC1016 from a single -5.2V power supply will bias the digital inputs for ECL levels, while operating from a dual 5V power supply will bias the digital inputs for TTL levels. All versions of the TDC1016 are 10-bit digital-to-analog converters, but are available with linearity specifications of either 8, 9, or 10 bits. The TDC1016 is patented under U.S. patent number 3283120 with other patents pending.
Applications
* Construction of video signals from digital data 3x or 4x NTSC or PAL color subcarrier frequency * CRT graphics displays, RGB, Raster, Vector * Waveform synthesis
Block Diagram
10 TTL INPUTS (20 ECL INPUTS) CLK (CLK) NDIS (NDIS) NFL NFH N2C VREF COMP A
65-1016-01
TTL/ECL DIGITAL INPUT BUFFERS
DATA LATCHED 10 10
CURRENT SWITCHES 10
R-2R RESISTOR NETWORK
AOUT
CLK
VREF
Rev. 1.0.0
TDC1016
PRODUCT SPECIFICATION
Functional Description
General Information
TTL/ECL buffers are used for all digital inputs to the TDC1016. Logic family compatibility depends upon the connection of power supplies. When single power supply (-5.2V) operation is employed, all data, clock, and disable inputs are compatible with differential ECL logic levels. All digital inputs become compatible with TTL levels when dual power supply (5.0V) operation is used. The internal 10-bit register latches data on the rising edge of the clock (CLK) pulse. Currents from the current sources are switched accordingly and combined in the resistor network to give an analog output voltage. The magnitude of the output voltage is directly proportional to the magnitude of the digital input word. The NFL and NFH inputs can be used to simplify system calibration by forcing the analog output voltage to either its zero-scale or full-scale value. The TDC1016 can be operated in binary, inverse binary, two's complement or inverse two's complement input data formats.
The internal operational amplifier of the TDC1016 is frequency stabilized by an external 1 mF tantalum capacitor connected between the COMP pin and VEE. A minimum of 1 mF is adequate for most applications, but 10 microfarads or more is recommended for optimum performance. The negative side of this capacitor should be connected to VEE.
Controls
The NDIS inputs are used to disable the TDC1016 by forcing its output to the zero-scale value (current sources off). The NDIS inputs are asynchronous, active without regard to the CLK inputs. The other digital control inputs are synchronous, latched on the rising edge of the CLK pulse. The rising edge of the CLK pulse transfers data from the input lines to the internal 10-bit register. In TTL mode, the inverted inputs for CLK, DATA, and NDIS are inactive and should be left open. The Input Coding Table illustrates the function of the digital control inputs. A two's complement mode is created by activating N2C with a Logic 0 When NFH and NFL are both activated with a Logic 0 the input data to the 10-bit register is inverted.
Power
The TDC1016 can be operated from a single -5.2V power supply or from a dual 5.0V power supply. For single power supply operation, VCC is connected to DGND and all inputs to the device become ECL compatible. When VCC is tied to +5.0V, the inputs are TTL compatible. The return path for the output from the 10 current sources is AGND. The current return path for the digital section is DGND. DGND and AGND should be returned to system power supply ground by way of separate conductive paths to prevent digital ground noise from disturbing the analog circuitry of the TDC1016. All AGND pins must be connected to system analog ground.
Data Inputs
Data inputs are ECL compatible when single power supply operation is employed. The J5 and C2 packages allow for differential ECL inputs while the J7 and B7 packages have only single-ended inputs. When differential ECL data is used, any data input can be inverted simply by reversing the connections to the true and inverted data input pins. All inverted input pins should be left open if single-ended ECL or TTL modes are used. All data inputs have an internal 40 KW pullup resistor to VCC.
Analog Output
The analog output voltage is negative with respect to AGND and varies proportionally with the magnitude of the input data word. The output resistance at this point is 80W, nominally.
Reference
The reference input is normally set to -1.0V with respect to AGND. Adjusting this voltage is equivalent to adjusting system gain The temperature stability of the TDC1016 analog output (AOUT) depends primarily upon the temperature stability of the applied reference voltage
No Connects
There are several pins labeled no connect (NC) on the TDC1016 J5 and C2 packages, which have no connections to the chip. These pins should be left open.
2
PRODUCT SPECIFICATION
TDC1016
Pin Assignments
40 Lead Ceramic DIP
NC VEE COMP VREF AGND AGND AOUT AGND VCC DGND NDIS CLK CLK NDIS (MSB) D1 (MSB) D1 N2C D2 D2 NFH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
NC NC NC D10 (LSB) D10 (LSB) D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 NFL
24 Lead Ceramic DIP
VREF AGND AGND AOUT AGND VCC DGND NDIS CLK (MSB) D1 N2C D2
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
COMP VEE D10 (LSB) D9 D8 D7 D6 D5 D4 D3 NFL NFH
65-1016-02
Pin Descriptions
Pin Number Pin Name Power VCC VEE AGND DGND Reference VREF COMP Controls NDIS NDIS CLK CLK N2C NFH NFL Data Inputs D1-D10 16, 19, 23, 25, 27, 29, 31, 33, 35, 37 10, 12, 15-20, 27, 22 TTL/ECL Data Bits 1-10. D1 is the MSB, D10 is the LSB. 11 14 12 13 17 20 21 8 -- 9 -- 11 13 14 TTL/ECL ECL TTL/ECL ECL TTL/ECL TTL/ECL TTL/ECL Not Disable. Not Disable (Inv). Clock. Clock (Inv). Not Two's Complement. Not Force HIGH. Not Force LOW. 4 3 1 24 -1.0V 1mF Reference Voltage In. Compensation. 9 2 5, 6, 8 10 6 23 2, 3, 5 7 +5.0V -5.0V 0.0V 0.0V Positive Supply Voltage. Negative Supply Voltage. Analog Ground. Digital Ground. 40-Lead 24-Lead Value Pin Function Description
3
TDC1016
PRODUCT SPECIFICATION
Pin Descriptions (continued)
Pin Number Pin Name D1-D10 40-Lead 15, 18, 22, 24, 26, 28, 30, 32, 34, 36 7 1, 38-40 24-Lead -- Value ECL Pin Function Description Data Bits 1-10 (Inv). D1 is the MSB, D10 is the LSB.
Analog Output AOUT No Connection NC -- Open No Connection 4 0V-1V Analog Output Voltage
Absolute Maximum Ratings (beyond which the device wille be damaged)1
Parameter Supply Voltages VCC (measured to DGND) VEE (measured to AGND) AGND (measured to DGND) Input Voltages Digital (measured to DGND) Reference (measured to AGND) Output Applied Voltage (measured to AGND)2 Short-Circuit Duration Temperature Operating, Ambient Operating, Junction Lead, Soldering (10 seconds) Storage -65 +125 +175 +300 +150 C C C C -2.0 +2.0 Indefinite V -7.0 -1.5 +7.0 +0.5 V V -0.5 -7.0 -0.5 +7.0 +0.5 +0.5 V V V Min. Max. Unit
Notes: 1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied. 2. Applied voltage must be current limited to specified range.
4
PRODUCT SPECIFICATION
TDC1016
Operating Conditions
Temperature Range Standard Symbol VCC VEE VAGND tPWL tPWH tS tH VIL VIH VREF CCOMP TA TC Parameter Positive Supply Voltage Negative Supply Voltage Analog Ground Voltage (Measured to DGND) CLK Pulse Width, LOW CLK Pulse Width, HIGH Input Register Set-up Time Input Register Hold Time Logic 0 Logic 1 Reference Voltage Compensation Capacitor Ambient Temperature Case Temperature TTL Mode ECL Mode TTL Mode ECL Mode 2.0 -1.0 -0.8 1.0 0 70 -55 125 -1.0 -1.2 TTL Mode ECL Mode TTL Mode ECL Mode Min. 4.75 -0.25 -4.5 -0.1 15 15 20 25 2 DGND 0.8 -1.67 VCC 2.01 -1.0 -0.8 1.0 -1.0 1.2 Nom. 5.0 0.0 -5.0 0.0 Max. 5.25 0.25 -5.5 0.1 Min. 4.50 -0.25 -4.5 -0.1 20 20 22 27 2 DGND 0.8 -1.67 VCC Extended Nom. 5.0 0.0 -5.0 0.0 Max. 5.50 0.25 -5.5 0.1 Unit V V V V ns ns ns ns ns V V V V V mF C C
Note: 1. VIH/NDIS = 2.2 Min.
DC Electrical Characteristics
Temperature Range Standard Symbol ICC IEE IREF IIL IIH COUT CIN ROUT Parameter Power Supply Current Power Supply Current Reference Input Current Logic 0 Input Current Logic 1 Input Current Output Capacitance Digital Input Capacitance Output Resistance Test Conditions TTL Mode, VCC = Max, VEE = Max TTL Mode, VCC = Max, VEE = Max1 VEE = Max, VREF = -10V TTL Mode, VCC = Max, VEE = Max ECL Mode, VCC = 0.0, VEE = Max TTL Mode, VCC = Max, VEE = Max ECL Mode, VCC = 0.0, VEE = Max AOUT to AGND (Figure 2) Any Digital Input to DGND AOUT to AGND (Figure 2) 70 20 -130 10 -1.0 -300 75 350 10 35 95 70 Extended 20 -150 10 -1.0 -300 75 350 10 35 95 mA mA mA mA mA mA mA pF pF W Min. Max. Min. Max. Unit
Note: 1. Return current from VEE flows through AGND.
5
TDC1016
PRODUCT SPECIFICATION
AC Electrical Characteristics
Temperature Range Standard Symbol FC tDS tSET Parameter Maximum Data Rate Data Turn on Delay Settling Time Test Conditions TTL Mode Full-Scale Output Step ECL Mode Full-Scale Output Step RL = 75 Ohms TDC1016-8 to 0.2% TDC1016-9 to 0.1% TDC1016-10 to .05% tRV Output 10% to 90% Risetime VEE = Nom., RL = 75W, Full-Scale Step Min. 20 17.8 30 30 35 40 5.5 Max. Extended Min. 20 17.8 30 30 35 40 5.5 Max. Unit MSPS MSPS ns ns ns ns ns
Timing Diagram
tS DATA CONTROLS CLOCK tPWL
1
tH
tPWH
CLOCK 1/2 LSB
OUTPUT
1/2 LSB tDS tSET
65-1016-06
NOTE: 1. Differential ECL mode only
Figure 1. Timing Diagram
System Performance Characteristics
Temperature Range Standard Parameter RES ELI, ELD Resolution Linearity Error Integral and Differential, Independent Based Full-Scale Output Voltage Zero-Scale Output Voltage Differential Phase Differential Gain Glitch Energy (Area) Glitch Voltage Test Conditions All TDC1016 Devices TDC1016-8 TDC1016-9 TDC1016-10 VEE = Nom, RL 10kW, VREF = -1.000V VEE = Nom, RL 10 kW, VREF = -1.000V NTSC 4x Subcarrier1 NTSC 4x subcarrier1 RL = 50W, Midscale RL = 50W, Midscale -0.95 Min. Max. 10 0.2 0.1 0.075 -1.05 15 1.0 1.5 125 35 -0.95 -1.05 15 1.0 1.5 125 35 Extended Min. Max. 10 0.2 0.1 Unit Bits % FS % FS % FS V mV Degrees % pV-sec mV
VOFS VOZS DP DG GE GV
Note: 1. In excess of theoretical DP and DG due to quantizing error.
6
PRODUCT SPECIFICATION
TDC1016
Equivalent Circuits
AGND
ROUT 801/21
COUT
AOUT
INPUT DATA DEPENDENT CURRENT SINK
VEE NOTE: 1. 751/2 requires outside trim
65-1016-03
Figure 2. Analog Output Equivalent Circuit, TTL and ECL Mode
VCC (+5.0V) 40K 50K 35K
VCC (+5.0V)
40K
50K
DGND 13K DATA DATA I=0 DGND VEE VEE
65-1016-04
6.7K
DATA 37K I = 75A
Figure 3. Digital Input Equivalent Circuit, TTL Mode
Figure 4. Digital Input Equivalent Circuit, ECL Mode
7
TDC1016
PRODUCT SPECIFICATION
Input Coding Table
NDIS 0 1 1 1 1 1 1 1 1 1 1 N2C x 1 1 1 1 0 0 0 0 x x NFH x 1 1 0 0 1 1 0 0 0 1 NFL x 1 1 0 0 1 1 0 0 1 0 Data xxxxxxxxxx 1111111111 0000000000 1111111111 0000000000 0111111111 1000000000 0111111111 1000000000 xxxxxxxxxx xxxxxxxxxx Output 0.0 0.0 -1.0 -1.0 0.0 0.0 -1.0 -1.0 0.0 0.0 -1.0 Description Output Disabled Binary (Default State for TTL Mode Control) Inputs Open Inverse Binary Two's Complement Inverse Two's Complement Force HIGH Force LOW
Notes: 1. For TTL, 0.0 < VIL < +0.8V is Logic 0. 2. For TTL, +2.0 < VIH < +5.0V is Logic 1. 3. For ECL, -1.85 < VIL < -1.67V is Logic 0. 4. For ECL, -1.0 < VIH < -0.8V is Logic 1. 5. x = don't care.
Applications Discussion
Calibration
The TDC1016 is calibrated by adjusting the voltage reference to give the desired full-scale output voltage. The current switches can be turned on either by loading the data register with full-scale data or by bringing the NFH input to a logic zero. Note that all 10 current switches are activated by the NFH input and the resulting full-scale output voltage will be greater than if the system used only eight or nine bits for full-scale data.
The TDC1016 output and currents from the SYNC and BLANKING inputs are summed and amplified by the HA2539 wide-band operational amplifier. Note the careful power supply decoupling at the power input pins of the amplifier. The output of the circuit is a composite video signal with SYNC and BLANKING levels coming from external sources. This technique allows the TDC1016 to use its entire dynamic range for the video information while pulses are added by other means. The reference for the TDC1016 is generated by dividing the output voltage from a two-terminal band-gap voltage reference. System gain is calibrated by adjusting variable resistor R1. Analog and digital grounds should be routed back to system power supply ground by separate paths.
Typical Application
The Typical Interface Circuit (Figure 5) shows the TDC1016 in a typical application, reconstructing video signals from digital data. Television timing signals, SYNC and BLANKING, are added by injecting current from the Wilson current source into a resistor divider circuit at the output of the TDC1016.
8
PRODUCT SPECIFICATION
TDC1016
+12V +5V C4 C1 12 16 19 23 25 TTL DATA INPUTS 27 29 31 33 35 37 9 10 DGND Q2 Q3 R4 Q1 U1 TDC1016 7 AOUT C6 R4 R21 +5V CR1 +12V R6 R12 C7 14 - 1 C5 R13 U3 + 10 3 C8 L2 C10 R9
65-1016-05
+ R14 R15 R16 R22 Q4 U4 R20 SYNC
CLOCK
R17
CLK VCC D1 MSB D2 D3 D4 D5 D6 D7 D8 D9
R18
Q5 U4 BLANKING
+5V D10 LSB VCC COMP VREF AGND 3 +4 2 + 5,6,8 C2 R11 C3 R1 GAIN R2 OFFSET R3 U2 -5V R12
R7 C9 L1 8 R10 COMPOSITE VIDEO OUT R8
-12V
Figure 5. Typical Interface Circuit
Table 1. Bill of Materials
Resistors R1 R2 R3 R4 R5 R6 R7 R8, R9 R10 R11, R12 R13 R14, R15 R16, R22 R17, R18 R19 R20, R21 5K 1K 1K 43 33 330 750 10 75 10K 220 100 390 2K 1K 1K 1/4W 1/4W 1/4W 1/4W 1/4W 1/4W 1/4W 1/4W 1/4W 1/4W 1/4W 1/4W 1/4W 1/4W 1/4W 1/4W 10-turn 10-tum 5% 5% 5% 5% 5% 5% 2% 5% 5% 5% 5% 10-turn 5% 5% RF Chokes L1, L2 Ferrite Beads Capacitors C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 0.01mF 1.0mF 1.0mF 2.2mF 0.1mF 2-5pF 0.1mF 0.1mF 0.1mF 0.1mF 50V 10V 10V 25V 50V 50V 50V 50V 50V 50V Integrated Circuits U1 U2 U3 U4 TDC1016 LM113 HA2539 SN7404 Transistors Q1 Q2 Q3 Q4 Q5 2N2907 2N2907 2N2907 2N6660 2N6660 Diodes CR1 1N4001
9
TDC1016
PRODUCT SPECIFICATION
Mechanical Dimensions
40 Lead Sidebrazed Ceramic DIP
Inches Min. A b1 b2 c1 D E e eA L Q S1 S2 .120 .014 .040 Max. .175 .023 .065 Millimeters Min. 3.05 .360 1.02 Max. 4.44 .580 1.65 7 2 7 Notes: Notes 1. Index area: a notch or a pin one identification mark shall be located adjacent to pin one. The manufacturer's identification shall not be used as pin one identification mark. 2. The minimum limit for dimension "b2" may be .023(.58mm) for leads number 1, 20, 21, and 40 only. 3. Dimension "Q" shall be measured from the seating plane to the base plane. 4. The basic pin spacing is .100 (2.54mm) between centerlines. Each pin centerline shall be located within .010 (.25mm) of its exact longitudinal position relative to pins 1 and 40. 5. Applies to all four corners (leads number 1, 20, 21, and 40). 6. "eA" shall be measured at the centerline of the leads. 7. All leads - Increase maximum limit by .003(.08mm) measured at the center of the flat when lead finish is applied. 8. Thirty-eight spaces.
Symbol
.008 .015 1.970 2.030 .575 .610 .100 BSC .600 BSC .125 .200 .025 .060 .005 -- .005 --
.200 .380 50.04 51.56 14.60 15.49 2.54 BSC 15.24 BSC 3.18 5.08 .63 1.52 .13 -- .13 --
4, 8 6 3 5
D 20 1
Note 1
E
S1
21
40 eA S2
A Q L b2 c1
e
b1
10
PRODUCT SPECIFICATION
TDC1016
Mechanical Dimensions (continued)
24 Lead Sidebrazed Ceramic DIP
Inches Min. A b1 b2 c1 D E e eA L Q S1 S2 .120 .014 .040 Max. .175 .023 .065 Millimeters Min. 3.05 .360 1.02 Max. 4.44 .580 1.65 7 2 7 Notes: Notes 1. Index area: a notch or a pin one identification mark shall be located adjacent to pin one. The manufacturer's identification shall not be used as pin one identification mark. 2. The minimum limit for dimension "b2" may be .023(.58mm) for leads number 1, 12, 13, and 24 only. 3. Dimension "Q" shall be measured from the seating plane to the base plane. 4. The basic pin spacing is .100 (2.54mm) between centerlines. Each pin centerline shall be located within .010 (.25mm) of its exact longitudinal position relative to pins 1 and 24. 5. Applies to all four corners (leads number 1, 12, 13, and 24). 6. "eA" shall be measured at the centerline of the leads. 7. All leads - Increase maximum limit by .003(.08mm) measured at the center of the flat when lead finish is applied. 8. Twenty-two spaces.
Symbol
.008 .015 1.180 1.220 .575 .610 .100 BSC .600 BSC .125 .200 .025 .060 .005 -- .005 --
.200 .380 29.97 30.99 14.60 15.49 2.54 BSC 15.24 BSC 3.18 5.08 .630 1.52 .13 -- .13 --
4, 8 7 3 5
D 12 1 Note 1
E
13 S1
24
eA S2
A Q L
b2
e
b1
c1
11
TDC1016
PRODUCT SPECIFICATION
Ordering Information
Product Number TDC1016J5CX TDC1016J5AX TDC1016J7CX TDC1016J7AX Temperature Range STD - TA = 0C to 70C EXT - TC = -55C to 125C STD - TA = 0C to 70C EXT - TC = -55C to 125C Screening Commercial High Reliability Commercial High Reliability Package 40 Pin Ceramic 40 Pin Ceramic 24 Pin Ceramic 24 Pin Ceramic Package Marking 1016J5CX 1016J5AX 1016J7CX 1016J7AX
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS90001016 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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